in this role, you are supposed to be a member of soc architecture team.
you will work with software and hardware engineering groups to define the next-generation high performance network interface controllers (nics).
you will help build up a system-level c++ simulator for the target soc, with new features implemented. you will use the simulator to study a range of performance, power, and cost trade-offs.
we expect you can
* write c++ to implement new features and functional blocks in the simulator
* analyze the workload of high-performance datacenter network to define the architecture of high-performance nic
* be responsible for drafting the architecture and microarchitecture specification
* closely collaborate with the rtl design team for the microarchitecture design and performance correlation
* work with software team to define the system architecture of next-generation high-performance network protocol stack and its applications
* work in a cross-team and open-communication culture to collaborate with multiple teams in both the us and china to delegate tasks, set deadlines and ensure deliverables.
bs/ms/ph.d. in electronics engineering with minimum of 5 years of chip design experiences
* strong c++ coding skill (systemc is a good plus)
* strong background in computer architecture, including cpu, cache, dram, on-chip interconnect, nic, pcie and other i/os
* hands on experience in performance modeling and analysis (systemc tlm is a good plus)
* experience in workload analysis and characterization
* experience in working with other to draft architecture and microarchitecture specification
* design expertise in network area is a good plus, including switches, routers and network interface card.
* hands on experience in high-performance nics is a good plus, including rdma (rocev2 or iwarp) and toe
* familiarity with tcp/ip protocol stack, as well as hands on experience on kernel or user-space networking stack is a good plus;
- 中国浙江省杭州市滨江区 网商路699号