in this role, you are supposed to be a member of soc rtl design team.
you will work with software and hardware engineering groups to design the next-generation high performance network interface controllers (nics).
we expect you can:
* write detail specifications and define micro-architecture of the design
* implement high performance design using high-quality rtl coding techniques
* work with performance modeling/analysis team to enhance the performance
* collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug
* work with the physical design team in aiding the implementation of the functional blocks
* work with multiple design groups (china, us) to shape future design
* support the post silicon team to bring up silicon in the lab
* work with the software team to ensure product meets customer use cases
bs/ms in electronics engineering with minimum of 10 years of rtl design expriences
* strong verilog/systemverilog rtl coding skill、
* experience in micro architecture/resoruce tradeoff, soc integration, cdc, lint
* experience with performing synthesis, timing analysis/timing closure, formal verification/lec, dft
* design expertise in network area is a good plus, including switches, routers and network interface card.
* hands on experience in high-performance nics is a good plus, including rdma (rocev2 or iwarp) and toe
* knowledge with cpu/gpu/dsp/ai accelerator architecture design
* familiarity with revision control concepts and tools (e.g. git)
* experience with perl, tcl or other scripting language.
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